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31
CYM1831
64K x 32 Static RAM Module
Features
* High-density 2-Mbit SRAM module * 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 * High-speed CMOS SRAMs -- Access time of 15 ns * Low active power -- 5.3W (max.) * SMD technology * TTL-compatible inputs and outputs * Low profile -- Max. height of 0.50 in. * Small PCB footprint -- 1.2 sq. in. on an epoxy laminate board with pins. Four chip selects (CS1, CS2, CS3, and CS4) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate Chip Selects (CSN) and Write Enable (WE) inputs are both LOW. Data on the input/output pins (I/OX) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Selects (CSN) LOW and Output Enable (OE) LOW while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data input/output pins (I/OX). The data input/output pins stay in the high-impedance state when Write Enable (WE) is LOW or the appropriate chip selects are HIGH. Two pins (PD0 and PD1) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged.
Functional Description
The CYM1831 is a high-performance 2-Mbit static RAM module organized as 64K words by 32 bits. This module is constructed from eight 64K x 4 SRAMs in SOJ packages mounted
Logic Block Diagram
PD0 - OPEN PD1 - GND
16
Pin Configuration
ZIP/SIMM Top View
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
A0 -A15 OE WE
64K x 4 SRAM CS1 64K x 4 SRAM CS2 64K x 4 SRAM CS3 64K x 4 SRAM CS4
4
I/O0 - I/O3
64K x 4 SRAM
4
I/O4- I/O7
4
I/O8 - I/O11
64K x 4 SRAM
4
I/O12- I/O15
PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 CS3 NC GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND
GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 CS4 NC OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31
4
I/O16 - I/O19
64K x 4 SRAM
4
I/O20- I/O23
4
I/O24 - I/O27
64K x 4 SRAM
4
I/O28- I/O31
Cypress Semiconductor Corporation Document #: 38-05270 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised March 15, 2002
CYM1831
Selection Guide
1831-15 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 15 1120 160 1831-20 20 960 160 1831-25 25 720 160 1831-30 30 720 160 1831-35 35 720 160 1831-45 45 720 160
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -0.5V to +7.0V Output Current into Outputs (LOW) .............................20 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
1831-15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CS Power-Down Current[1] Automatic CS Power-Down Current[1] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, CSN < VIL VCC = Max., CSN > VIH, Min. Duty Cycle = 100% VCC = Max., CSN > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -20 -20 Min. 2.4 0.4 VCC 0.8 +20 +20 1120 320 160 2.2 -0.5 -20 -20 Max. 1831-20 Min. 2.4 0.4 VCC 0.8 +20 +20 960 320 160 2.2 -0.5 -20 -20 Max. 1831-25, 30, 35, 45 Min. 2.4 0.4 VCC 0.8 +20 +20 720 320 160 Max. Unit V V V V A A mA mA mA
Capacitance[2]
Parameter CINA CINB COUT Description Input Capacitance (A0-A15, WE, OE) Input Capacitance (CS) Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 80 15 20 Unit pF pF pF
Notes: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis.
Document #: 38-05270 Rev. **
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CYM1831
AC Test Loads and Waveforms
R1 481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255 R1 481 3.0V 90% GND < 5 ns 10% 90% 10% < 5 ns ALL INPUT PULSES
(a)
(b)
Equivalent to:
THE VENIN EQUIVALENT 167 1.73V OUTPUT
Switching Characteristics Over the Operating Range[3]
1831-15 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE LOW to High Z CS LOW to Low Z
[4]
1831-20
1831-25
1831-30
1831-35
1831-45
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit 15 15 3 15 8 0 8 0 0 6 15 10 10 2 2 10 8 2 3 0 7 20 15 15 2 2 15 12 2 3 0 10 8 25 20 20 2 2 20 15 2 3 0 13 0 10 3 13 30 25 25 2 2 25 15 2 3 0 15 3 20 10 0 15 3 15 35 30 30 2 2 25 20 2 3 0 20 20 20 3 25 15 0 15 3 20 45 40 40 2 2 30 20 2 3 0 20 25 25 3 30 20 0 20 3 20 30 30 3 35 20 0 20 35 35 3 45 30 45 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CS HIGH to High Z[4, 5]
[6]
WRITE CYCLE
Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[5]
Note: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested. 5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05270 Rev. **
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CYM1831
Switching Waveforms
Read Cycle No. 1 [7, 8]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No . 2[7, 9]
CS tACS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS tPU VCC SUPPLY CURRENT 50% DATA VALID tPD ICC 50% ISB tHZOE tHZCS tRC
HIGH IMPEDANCE
Notes: 7. WE is HIGH for read cycle. 8. Device is continuously selected, CS = VIL and OE= VIL. 9. Address valid prior to or coincident with CS transition LOW.
Document #: 38-05270 Rev. **
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CYM1831
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[6]
tWC ADDRESS tSCS CS tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED tLZWE HIGH IMPEDANCE tHD tAW tPWE tHA
Write Cycle No. 2 (CS Controlled)[6, 10]
tWC ADDRESS tSA CS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE DATA UNDEFINED tHD tHA tSCS
Note: 10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CSN WE OE H L L L X H L H X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect Mode Deselect/Power-Down
Document #: 38-05270 Rev. **
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CYM1831
Ordering Information
Speed 15 Ordering Code CYM1831PM-15C CYM1831PN-15C CYM1831PY-15C CYM1831PZ-15C 20 CYM1831PM-20C CYM1831PN-20C CYM1831PY-20C CYM1831PZ-20C 25 CYM1831PM-25C CYM1831PN-25C CYM1831PY-25C CYM1831PZ-25C 35 CYM1831PM-35C CYM1831PN-35C CYM1831PY-35C CYM1831PZ-35C 45 CYM1831PM-45C CYM1831PN-45C CYM1831PY-45C CYM1831PZ-45C Package Name PM01 PN01 PM01 PZ01 PM01 PN01 PM01 PZ01 PM01 PN01 PM01 PZ01 PM01 PN01 PM01 PZ01 PM01 PN01 PM01 PZ01 Package Type 64-Pin Plastic SIMM Module 64-Pin Plastic Angled SIMM Module 64-Pin Gold SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic SIMM Module 64-Pin Plastic Angled SIMM Module 64-Pin Gold SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic SIMM Module 64-Pin Plastic Angled SIMM Module 64-Pin Gold SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic SIMM Module 64-Pin Plastic Angled SIMM Module 64-Pin Gold SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic SIMM Module 64-Pin Plastic Angled SIMM Module 64-Pin Gold SIMM Module 64-Pin Plastic ZIP Module Commercial Commercial Commercial Commercial Operating Range Commercial
Document #: 38-05270 Rev. **
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CYM1831
Package Diagrams
64-Pin Plastic SIMM Module PM01
0.125 DIA. + 0.001 2 PLCS 3.845 3.855 3.580 3.588
0.330 MAX
0.400
0.525 MAX
0.250 0.080 0.250
PIN 1
0.050 TYP
0.62 R + 0.001 0.250 3.35 (64 PINS)
0.145 REF PIN 64
64-Pin Plastic Angled SIMM Module PN01
3.845/3.855 3.580/3.588 .330MAX
C1
C3
C5
C7
.397/.403 .245/.255
PIN1 .075/.085 .245/.255 3.348/3.352
.061/.063R .249/.251
64-Pin Plastic ZIP Module PZ01
Bottom View 3.640 3.660 0.330 MAX
0.050
0.050 0.120 0.150
C10
U1
C2 C4
U2
C6
U3
C8
U4
C9
.590/.600
0.500 MAX
0.008 0.014 0.135 0.165 0.015 0.025 0.250 TYP 0.100 TYP 0.050 TYP 0.100 TYP Pin 1 DIMENSIONS IN INCHES MIN. MAX.
Document #: 38-05270 Rev. **
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYM1831
Document Title: CYM1831 64K x 32 Static RAM Module Document Number: 38-05270 REV. ** ECN NO. 114171 Issue Date 3/19/02 Orig. of Change DSG Description of Change Change from Spec number: 38-M-00018 to 38-05270
Document #: 38-05270 Rev. **
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